1. Field of the Invention
The present invention relates to a charge transfer device which is suitable for use as a two-dimensional image sensor or the like, and more particularly, the invention relates to a charge transfer device which can be produced in a high density, also to a method of producing the same.
2. Description of the Prior Art
As is well known in the art, the four-phase drive system shown in FIG. 12, the three-phase drive system in FIG. 13, and the two-phase drive system in FIG. 14 are the most common charge transfer systems which are employed in charge transfer devices (CTDs) such as charge coupled devices (CCDs) used as two-dimensional image sensors. A 1.multidot.(1/2)-phase drive system is essentially the same as the two-phase drive system, the only difference being that one of the two phases in the two-phase drive system uses a DC potential.
When considering a unit of a bit configuration, one phase usually corresponds to one electrode in both the four-phase and three-phase drive systems. By contrast, in the two-phase drive system, one phase usually requires two electrodes in order to provide a built-in directionality of charge transfer.
Generally, the directionality of charge transfer is achieved by implanting an impurity such as Nb only under one transfer electrode within the same phase and thereby forming a potential barrier Vb as shown in FIG. 14.
With respect to the structure of electrodes, both the two-phase and four-phase drive systems permit the use of a two-layered structure, whereas the three-phase drive system requires a three-layered structure in order to maintain the equality of each bit. As a result, the two-phase or four-phase drive system is usually employed.
From the point of view of the maximum amount of charge transfer per unit area, the four-phase drive system provides the best characteristics because, as shown in FIG. 12, the storage area for a signal charge occupies more than 50% of the bit length and the effective potential difference can be provided by an amount equal to the clock amplitude Vc.
On the other hand, from the point of view of transfer efficiency, the two-phase drive system is the best choice because it permits an extended fringing electric field effect that determines the charge transfer in a high speed transfer operation. More specifically, in the two-phase drive system, since the directionality of charge transfer is formed as shown in FIG. 14, the fringing electric field effect acts throughout the period of charge transfer, which serves to prevent loss or back transfer of charge. Thus, the two-phase drive system provides a transfer efficiency superior to that achieved by any other drive system.
For the above-mentioned reasons, it is usual to employ the four-phase drive system for a slow speed transfer and the two-phase drive system for a high speed transfer.
In such a CCD, it is imperative to avoid an increase in the chip size. In order to increase the number of bits, therefore, the bit length must be made extremely short. A manner of accomplishing this in a two-dimension image sensor will be described.
As is well known, a two-dimension CCD image sensor consists of a plurality of pixels (photodiodes) arranged in a two-dimensional array, a plurality of rows of vertical shift registers for vertically transferring the signal charges accumulated at the pixels, and a horizontal shift register, usually a single row, for receiving the vertically transferred signal charges and transferring them in the horizontal direction for conversion into electrical signals.
Since the horizontal shift operation generally needs a high speed drive, the horizontal shift register uses the two-phase drive system, and has an electrode pattern as shown in FIG. 15. Encircled by a dashed line is an active region 20 which constitutes a CCD transfer channel in the horizontal shift register. A channel-stop region is formed outside the active region 20. Broken lines indicate first transfer electrodes 4, and solid lines second transfer electrodes 5. Clock signals .phi..sub.H1 and .phi..sub.H2 are applied via connections indicated by dotted lines to the transfer electrodes 4 and 5, respectively, through contact windows 22 indicated by marks "X".
The relationship between the bit length and the number of pixels in a horizontal row will be discussed. As the number of pixels increases, the bit length in a horizontal shift register (horizontal transfer section) is reduced. For example, in a 1/2-inch optical system, when the number of effective pixels in a horizontal row is 510, the bit length is about 12.8 .mu.m. Therefore, if the number of effective pixels is increased from 510 to 770, for example, the bit length will have to be reduced from about 12.8 .mu.m to about 8.5 .mu.m.
As can be seen from FIG. 15, the formation of four electrodes within the length of 8.5 .mu.m demands a very strict control in processing, and consequently it is difficult to form the contact windows 22 through which potentials are applied to the electrodes. These dimension restrictions are almost the limit that the current techniques can attain. A further increase in the number of pixels (and hence a further reduction in the bit length) is not attainable by current techniques.
The above discussion applies not only to two-dimension image sensors but also to one-dimension image sensors and delay lines.
Next, a vertical shift register will be discussed. Two-dimension CCD image sensors are classified, according to the relationship between the photodiodes and the vertical shift registers, into the interline transfer type and the frame transfer type. In the following, the interline transfer method which is currently dominant will be described.
FIG. 16 diagrammatically shows the configuration according to a CCD image sensor. As shown, vertical arrays of photodiodes PD are arranged alternately with vertical shift register arrays, and signal charges in the photodiodes PD are read out by the adjacent vertical shift registers. Leads from transfer electrodes .phi..sub.V1 -.phi..sub.V4 must be routed between the respective upper and lower photodiodes PD. When the transfer electrodes .phi..sub.V1 -.phi..sub.V4 of the vertical shift registers are formed in two layers, four electrodes are needed per bit, so that two photodiodes PD are required for one bit. In such a CCD image sensor, consequently, the four-phase drive system is employed. The manner of driving the sensor in the two-phase drive system is the same as that of the four-phase drive system. Therefore, in one read operation, signal charges from alternate photodiodes PD in the vertical direction are read out, or signal charges from the vertically adjacent two photodiodes PD are added for reading. It is not possible to read out individual signal charges from all photodiodes PD by a single read operation.
Thus, with a prior art charge transfer device, it is not possible to further increase the density.
Generally, even the slightest misalignment between the boundary of directionality and the boundary of the electrode will result in potential dips or barriers, causing a decrease in the transfer efficiency.
The most commonly known solution to this problem is the so-called offset gate CCD (C. Sequin and M. Tompsett, "CHARGE TRANSFER DEVICES", 1975, Academic Press). However, this configuration involves the following disadvantages.
(1) In a surface-channel CCD (SCCD), as shown in FIG. 6, the potential .phi..sub.m decreases as the gate insulating film thickness d.sub.ox increases, but the difference .phi..sub.m decreases with a decrease in the gate voltage V.sub.G. Unless the voltage is raised, a signal charge of a substantial amount cannot be attained for the low level side of the clock amplitude.
(2) In a buried-channel CCD (BCCD), as shown in FIG. 7, the potential .phi..sub.m increases with the increase of the gate insulating film thickness d.sub.ox, and the accumulation region is at the greater d.sub.ox side. On the other hand, as the gate insulating film thickness d.sub.ox increases, the amount of signal charge per unit gate voltage decreases, which is disadvantageous from the point of view of a transferable charge amount.
In such a minimum-sized CCD, the transfer directionality may be incorporated by ion-implanting impurities. However, with the prior art technique, it is not possible to implant impurities below the first-level electrode and automatically align the boundary of the implanted region with the edge of the first electrode. More specifically, the implantation below the first electrode must be performed before the formation of the first electrode, but it is usually not possible to align its position with the position of the subsequently formed electrode even by using a third layer as shown in FIG. 8, because the first electrode on the third layer needs to be removed.